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rev 1.0 K7P801866M 256kx36 & 512kx18 sram 1 k7p803666m nov. 1999 document title 256kx36 & 512kx18 synchronous pipelined sram the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any questions, please contact the samsung branch office near your office, call or cortact headquart ers. revision history rev. no. rev. 0.0 rev. 1.0 remark preliminary final history - preliminary specification release - final specification release draft date mar. 1999 nov. 1999
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 2 k7p803666m nov. 1999 pin description pin name pin description pin name pin description k, k differential clocks v ref hstl input reference voltage san synchronous address input m 1 , m 2 read protocol mode pins ( m 1 =v ss , m 2 =v dd ) dqn bi-directional data bus g asynchronous output enable sw synchronous global write enable ss synchronous select sw a synchronous byte a write enable tck jtag test clock sw b synchronous byte b write enable tms jtag test mode select sw c synchronous byte c write enable tdi jtag test data input sw d synchronous byte d write enable tdo jtag test data output zz asynchronous power down zq output driver impedance control v dd core power supply v ss gnd v ddq output power supply nc no connection 256kx36 & 512kx18 synchronous pipelined sram features organization part number cycle time access time 256kx36 k7p803666m-h25 4.0 2.0 k7p803666m-h21 5.0 2.0 k7p803666m-h20 5.0 2.5 512kx18 K7P801866M-h25 4.0 2.0 K7P801866M-h21 5.0 2.0 K7P801866M-h20 5.0 2.5 functional block diagram sa[0:17] or sa[0:18] ck ss sw sw x g 256kx36 data in zz dqx[1:9] (x=a, b, c, d) or (x=a, b) (x=a, b, c, d) or (x=a, b) k k ck or 512kx18 array r o w d e c o d e r column decoder write/read circuit register 0 1 data out register 1 read address register write address register latch sw register sw register latch sw x register sw x register ss register ss register 0 ? 256kx36 or 512kx18 organizations. ? 2.5v core/1.5v output power supply. ? hstl input and output levels. ? differential, hstl clock inputs k, k . ? synchronous read and write operation ? registered input and registered output ? internal pipeline latches to support late write. ? byte write capability(four byte write selects, one for each 9bits) ? synchronous or asynchronous output e nable. ? power down mode via zz signal. ? programmable impedance output drivers. ? jtag 1149.1 compatible test access port. ? 119(7x17)pin ball grid array package(14mmx22mm).
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 3 k7p803666m nov. 1999 package pin configurations (top view) k7p803666m(256kx36) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqc 8 dqc 9 v ss zq v ss dqb 9 dqb 8 e dqc 6 dqc 7 v ss ss v ss dqb 7 dqb 6 f v ddq dqc 5 v ss g v ss dqb 5 v ddq g dqc 3 dqc 4 sw c nc sw b dqb 4 dqb 3 h dqc 1 dqc 2 v ss nc v ss dqb 2 dqb 1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd 1 dqd 2 v ss k v ss dqa 2 dqa 1 l dqd 3 dqd 4 sw d k sw a dqa 4 dqa 3 m v ddq dqd 5 v ss sw v ss dqa 5 v ddq n dqd 6 dqd 7 v ss sa 0 v ss dqa 7 dqa 6 p dqd 8 dqd 9 v ss sa 1 v ss dqa 9 dqa 8 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc nc sa 14 sa 16 sa 3 nc zz u v ddq tms tdi tck tdo nc v ddq K7P801866M(512kx18) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqb 1 nc v ss zq v ss dqa 9 nc e nc dqb 2 v ss ss v ss nc dqa 8 f v ddq nc v ss g v ss dqa 7 v ddq g nc dqb 3 sw b nc nc nc dqa 6 h dqb 4 nc v ss nc v ss dqa 5 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb 5 v ss k v ss nc dqa 4 l dqb 6 nc nc k sw a dqa 3 nc m v ddq dqb 7 v ss sw v ss nc v ddq n dqb 8 nc v ss sa 0 v ss dqa 2 nc p nc dqb 9 v ss sa 1 v ss nc dqa 1 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc sa 18 sa 14 nc sa 3 sa 16 zz u v ddq tms tdi tck tdo nc v ddq
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 4 k7p803666m nov. 1999 function description the k7p803666m and K7P801866M are 9,437,184 bit synchronous pipeline mode sram. it is organized as 262,144 words of 36 bits(or 524,288 words of 18 bits)and is implemented in samsung s advanced cmos technology. single differential hstl level k clocks are used to initiate the read/write operation and all internal operations are self-timed . at the rising edge of k clock, all addresses, write enables, synchronous select and data ins are registered internally. data outs are updated from output registers edge of the next rising edge of the k clock. an internal write data buffer allows write data to fo llow one cycle after addresses and controls. the package is 119(7x17) ball grid array with balls on a 1.27mm pitch. during reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second edge, and data is captured in the output register and driven to the cpu during the second clock edge. ss is driven low during this cycle, signaling that the sram should drive out the data. during consecutive read cycles where the address is the same, the data output must be held constant without any glitches. this characteristic is because the sram will be read by devices that will operate slower than the sram frequency and will require mul ti- ple sram cycles to perform a single read operation. write(store) operation all addresses and sw are sampled on the clock rising edge. sw is low on the rising clock. write data is sampled on the rising clock, one cycle after write address and sw have been sampled by the sram. ss will be driven low during the same cycle that the address, sw and sw[ a:d] are valid to signal that a valid operation is on the address and control input. pipelined write are supported. this is done by using write data buffers on the sram that capture the write addresses on one writ e cycle, and write the array on the next write cycle. the "next write cycle" can actually be many cycles away, broken by a series of read cycles. byte writes are supported. the byte write signals sw[ a:d] signal which 9-bit bytes will be writen. timing of sw[ a:d] is the same as the sw signal. bypass read operation since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. for this case, the address comparator check to see if the new read address is the same as the contents of the stored write address latch. if the contents match, the read data must be supplied from the store d write data latch with standard read timing. if there is no match, the read data comes from the sram array. the bypassing of the sram array occurs on a byte by byte basis. if one byte is written and the other bytes are not, read data from the last written w ill have new byte data from the write data buffer and the other bytes from the sram array. mode control there are two mode control select pins (m 1 and m 2 ) used to set the proper read protocol. this sram supports single clock pipelined operating mode. for proper specified device operation, m 1 must be connected to v ss and m 2 must be connected to v dd . these mode pins must be set at power-up and must not change during device operation. programmable impedance output buffer operation this hstl late write sram has been designed with programmable impedance output buffers. the srams output buffer impedance can be adjusted to match the system data bus impedance, by connecting a external resistor (rq) between the zq pin of the sram and v ss . the value of rq must be five times the value of the intended line impedance driven by the sram. for example, a 250 w resistor will give an output buffer impedance of 50 w . the allowable range of rq is from 175 w to 350 w . internal circuits evaluate and periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. one e valu- ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the optimum level. impedance updates occur when the sram is in high-z state, and thus are triggered by write and deselect operations . updates will also be triggered with g high initiated high-z state, providing the specified g setup and hold times are met. imped ance match is not instantaneous upon power-up. in order to guarantee optimum output driver impedance, the sram requires a minimum number of non-read cycles (1,024) after power-up. the output buffers can also be programmed in a minimum impedance configura- tion by connecting zq to v ss or v dd . power-up/power-down supply voltage sequencing the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynchronous zz pin high. during sleep mode, all other inputs are ignor ed and outputs are brought to a high-impedance state. sleep mode current and output high-z are guaranteed after the specified sleep mode enable time. during sleep mode the memory array data content is preserved. sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated . normal operations can be resumed by bringing the zz pin low, but only after the specified sleep mode recovery time. read operation
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 5 k7p803666m nov. 1999 truth table k zz g ss sw sw a sw b sw c sw d dqa dqb dqc dqd operation x h x x x x x x x hi-z hi-z hi-z hi-z power down mode. no operation x l h x x x x x x hi-z hi-z hi-z hi-z output disabled. - l l h x x x x x hi-z hi-z hi-z hi-z output disabled. no operation - l l l h x x x x d out d out d out d out read cycle - l x l l h h h h hi-z hi-z hi-z hi-z no bytes written - l x l l l h h h d in hi-z hi-z hi-z write first byte - l x l l h l h h hi-z d in hi-z hi-z write second byte - l x l l h h l h hi-z hi-z d in hi-z write third byte - l x l l h h h l hi-z hi-z hi-z d in write fourth byte - l x l l l l l l d in d in d in d in write all bytes absolute maximum ratings stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit note core supply voltage relative to v ss v dd -0.5 to 3.0 v output supply voltage relative to v ss v ddq -0.5 to 3.0 v voltage on any i/o pin relative to v ss v term -0.5 to v dd +0.5 v output short-circuit current i out 25 ma operating temperature t opr 0 to 70 c storage temperature t stg -55 to 125 c recommended dc operating conditions parameter symbol min typ max unit note core power supply voltage v dd 2.35 2.5 2.65 v output power supply voltage v ddq 1.4 1.5 1.6 v input high level v ih v ref +0.1 - v ddq +0.3 v input low level v il -0.3 - v ref -0.1 v input reference voltage v ref 0.6 v ddq /2 2v ddq /3 v clock input signal voltage v in -clk -0.3 - v ddq +0.3 v clock input differential voltage v dif -clk 0.1 - v ddq +0.6 v clock input common mode voltage v cm -clk 0.6 v ddq /2 2v ddq /3 v
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 6 k7p803666m nov. 1999 pin capacitance note : periodically sampled and not 100% tested.(dv=0v, f=1mhz) parameter symbol typ max unit input capacitance c in - 4 pf output capacitance c out - 6 pf dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 10% @v oh =v ddq /2 for 175 w rq 350 w . 4. |i ol |=(v ddq /2)/(rq/5) 10% @v ol =v ddq /2 for 175 w rq 350 w . 5. programmable impedance output buffer mode. the zq pin is connected to v ss through rq. 6. minimum impedance output buffer mode. the zq pin is connected to v ss or v dd . parameter symbol min max unit note average power supply operating current-x36 (v in =v ih or v il , zz & ss =v il ) i dd4 i dd5 - 600 550 ma 1, 2 average power supply operating current-x18 (v in =v ih or v il , zz & ss =v il ) i dd4 i dd5 - 550 500 ma 1, 2 power supply standby current (v in =v ih or v il , zz=v ih ) i sbzz - 60 ma 1 active standby power supply current (v in =v ih or v il , ss =v ih , zz=v il ) i sbss - 200 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 m a output leakage current (v out =v ss or v ddq , dq in high-z) i lo -1 1 m a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v 3, 5 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4, 5 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v 6 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 6 output high voltage(i oh =-6ma) v oh3 v ddq -0.4 v ddq v 6 output low voltage(i ol =6ma) v ol3 v ss 0.4 v 6
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 7 k7p803666m nov. 1999 z0=50 w 50 w 0.75v *capacitive load consists of all components ac test conditions note : parameters are tested with rq=250 w and v ddq =1.5v. parameter symbol value unit core power supply voltage v dd 2.35~2.65 v output power supply voltage v ddq 1.4~1.6 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 1.0/1.0 ns input and out timing reference level 0.75 v clock input timing reference level cross point v ac test output load dout of the tester environment 20 pf* ac characteristics parameter symbol -25 -21 -20 unit note min max min max min max clock cycle time t khkh 4.0 - 5.0 - 5.0 - ns clock high pulse width t khkl 1.2 - 1.2 - 1.2 - ns clock low pulse width t klkh 1.2 - 1.2 - 1.2 - ns clock high to output valid t khqv - 2.0 - 2.0 - 2.5 ns clock high to output hold t khqx 0.5 - 0.5 - 0.5 - ns address setup time t avkh 0.5 - 0.5 - 0.5 - ns address hold time t khax 0.75 - 0.75 - 0.75 - ns write data setup time t dvkh 0.5 - 0.5 - 0.5 - ns write data hold time t khdx 0.75 - 0.75 - 0.75 - ns sw , sw [a:d] setup time t wvkh 0.5 - 0.5 - 0.5 - ns sw , sw [a:d] hold time t khwx 0.75 - 0.75 - 0.75 - ns ss setup time t svkh 0.5 - 0.5 - 0.5 - ns ss hold time t khsx 0.75 - 0.75 - 0.75 - ns clock high to output hi-z t khqz - 2.0 - 2.0 - 2.5 ns clock high to output low-z t khqx1 0.5 - 0.5 - 0.5 - ns g high to output high-z t ghqz - 2.0 - 2.0 - 2.5 ns g low to output low-z t glqx 0.5 - 0.5 - 0.5 - ns g low to output valid t glqv - 2.0 - 2.0 - 2.0 ns zz high to power down(sleep time) t zze - 8.0 - 10.0 - 10.0 ns zz low to recovery(wake-up time) t zzr - 8.0 - 10.0 - 10.0 ns
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 8 k7p803666m nov. 1999 timing waveforms of normal active cycles ( ss controlled, g =low) 1 2 3 4 5 6 7 8 k san ss sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a 4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 1 d 3 d 4 q 5 q 4 timing waveforms of normal active cycles ( g controlled, ss =low) 1 2 3 4 5 6 7 8 k san g sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a4 being a match from the l ast write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 2 q 1 d 3 d 4 q 5 q 4 q 2 t khkh t khax t avkh t khkl t klkh t khsx t svkh t wvkh t khwx t wvkh t khwx t khqx1 t khqx t wvkh t khwx t khqv t khdx t khqz t dvkh t khdx t khkh t ghqz t glqx t glqv
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 9 k7p803666m nov. 1999 timing waveforms of standby cycles 1 2 3 4 5 6 7 8 k san ss sw sw x dqn zz a 2 a 1 a 2 a 3 q 1 q 2 q 1 a 1 t khkh t zze t zzr t khqv t khqv
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 10 k7p803666m nov. 1999 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible teat access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg- ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo m 2 m 1 tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 11 k7p803666m nov. 1999 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 256kx36 0000 00110 00100 xxxxxx 00001001110 1 512kx18 0000 00111 00011 xxxxxx 00001001110 1 boundary scan exit order(x36) 36 3b sa 9 sa 8 5b 35 37 2b nc sa 17 6b 34 38 3a sa 10 sa 7 5a 33 39 3c sa 11 sa 6 5c 32 40 2c sa 12 sa 5 6c 31 41 2a sa 13 sa 4 6a 30 42 2d dqc 9 dqb 9 6d 29 43 1d dqc 8 dqb 8 7d 28 44 2e dqc 7 dqb 7 6e 27 45 1e dqc 6 dqb 6 7e 26 46 2f dqc 5 dqb 5 6f 25 47 2g dqc 4 dqb 4 6g 24 48 1g dqc 3 dqb 3 7g 23 49 2h dqc 2 dqb 2 6h 22 50 1h dqc 1 dqb 1 7h 21 51 3g sw c sw b 5g 20 52 4d zq g 4f 19 53 4e ss k 4k 18 54 4g nc k 4l 17 55 4h nc sw a 5l 16 56 4m sw dqa 1 7k 15 57 3l sw d dqa 2 6k 14 58 1k dqd 1 dqa 3 7l 13 59 2k dqd 2 dqa 4 6l 12 60 1l dqd 3 dqa 5 6m 11 61 2l dqd 4 dqa 6 7n 10 62 2m dqd 5 dqa 7 6n 9 63 1n dqd 6 dqa 8 7p 8 64 2n dqd 7 dqa 9 6p 7 65 1p dqd 8 zz 7t 6 66 2p dqd 9 sa 3 5t 5 67 3t sa 14 sa 2 6r 4 68 2r sa 15 sa 16 4t 3 69 4n sa 0 sa 1 4p 2 70 3r m 1 m 2 5r 1 boundary scan exit order(x18) 26 3b sa 9 sa 8 5b 25 27 2b nc sa 17 6b 24 28 3a sa 10 sa 7 5a 23 29 3c sa 11 sa 6 5c 22 30 2c sa 12 sa 5 6c 21 31 2a sa 13 sa 4 6a 20 dqa 9 6d 19 32 1d dqb 1 33 2e dqb 2 dqa 8 7e 18 dqa 7 6f 17 34 2g dqb 3 dqa 6 7g 16 dqa 5 6h 15 35 1h dqb 4 36 3g sw b 37 4d zq g 4f 14 38 4e ss k 4k 13 39 4g nc k 4l 12 40 4h nc sw a 5l 11 41 4m sw dqa 4 7k 10 42 2k dqb 5 dqa 3 6l 9 43 1l dqb 6 44 2m dqb 7 dqa 2 6n 8 45 1n dqb 8 dqa 1 7p 7 zz 7t 6 46 2p dqb 9 sa 3 5t 5 47 3t sa 14 sa 2 6r 4 48 2r sa 15 49 4n sa 0 sa 1 4p 3 50 2t sa 18 sa 16 6t 2 51 3r m 1 m 2 5r 1 scan register definition part instruction register bypass register id register boundary scan 256kx36 3 bits 1 bits 32 bits 70 bits 512kx18 3 bits 1 bits 32 bits 51 bits note : 1. pin 2b is a no connection pin to internal chip. this pin is a place holder for 16m part and the scanned data is fixed to "0" for this 8m part. 2. pins 4g and 4h are no connection pin to internal chip. the scanned data are fixed to "0" and "1" respectively.
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 12 k7p803666m nov. 1999 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 2.35 2.5 2.65 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.7 v output high voltage(i oh =-2ma) v oh 2.0 - v dd v output low voltage(i ol =2ma) v ol v ss - 0.4 v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns jtag ac test conditions note : 1. see sram ac test output load on page 7. parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.25 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
rev 1.0 K7P801866M 256kx36 & 512kx18 sram 13 k7p803666m nov. 1999 119 bga package dimensions 0.750 0.15 1.27 1.27 12.50 0.10 0.60 0.10 0.60 0.10 1.50ref c1.00 c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. indicator of ball(1a) location

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